Use of digital power amplifiers (DPAs) is desirable in transceiver systems (for use in wireless mobile terminals/stations and base stations) within a communication system to enhance efficiency, reduce costs and reduce size. DPAs typically include two stages—a driver stage and an output stage. The output stage is based on switch mode power amplifiers—an architecture that requires high speed devices.
The driver stage receives a pulsed digital signal which represents the modulated/coded signal. Such modulated/coded signals may be generated in accordance with any format, standard or specification, such as Global System for Mobile (GSM), Code Division Multiple Access (CDMA), Universal Mobile Telecommunication System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX), and the like, as well as others known to those skilled in the art.
A typical digital power amplifier output stage includes a power switch transistor driven by the pulsed waveform output from the driver stage. As frequency of operation increases, the amplifier's efficiency and response is affected. Switching speed of the power transistor (within the output stage) is limited by parasitic capacitances (gate-source capacitance, gate-drain capacitance and drain-source capacitance). These capacitances are generally proportional to the size of the transistor. Higher power transistors require larger dimensions, which fundamentally increases capacitance which also reduces efficiency at higher frequencies. As a result, for high power, high frequency DPAs, it is desirable to utilize transistors with a high power density and low parasitic capacitances (to decrease the charging/discharging time constant resulting from gate capacitances) as well as losses through output capacitance (drain-source capacitance).
Though driving power depends on switching frequency, it is independent of source impedance. However, the switching speed of the power transistor (within the output stage) is limited by its source impedance (i.e., the output impedance of the driver). As a result, output impedance of the driver stage becomes a crucial design parameter to consider when attempting to optimize the overall transmitter system efficiency. Various prior art attempts to increase efficiency, such as those involving 50 ohm impedance drivers, adversely affect the switching speed and power efficiency when power transistors are driven by pulsed digital signals.
Accordingly, there is a need for a digital power amplifier that includes a low output impedance driver to allow increased frequency operation and efficiency.